Deriving Cost Functions from Cell Libraries and Real IC’s to real Area-Power-Delay Trade-off in Early Stages of Logic Synthesis. – Hardware-Software Prototypes and Solutions Lab (CEPHIS)

Authors: Riera, J., Carrabina, J., Velasco, A.J., y Ribas, Ll.

Citation Key: 1159

COinS Data

ISSN: 0165-6074

Pagination: 119-122

Publication Language: eng

Journal: Journal of Systems Architecture

Volume: 43

Year of Publication: 1997