Physics-Based Compact Modeling and Circuit-Level Integration of Graphene FETs for Emerging Applications

For decades, silicon CMOS technology has been the backbone of the semiconductor industry, enabling continuous scaling and integration. Yet, as device dimensions approach the atomic limit, fundamental constraints such as quantum effects, power dissipation, and variability increasingly hinder further progress. This has accelerated the exploration of alternative materials to complement or extend CMOS.

Among them, graphene stands out due to its exceptional carrier mobility, thermal conductivity, mechanical robustness, and compatibility with flexible substrates. While its absence of a bandgap makes it unsuitable for digital logic, Graphene Field-Effect Transistors (GFETs) hold strong potential in domains such as hybrid CMOS–GFET biosensors, analog and radio-frequency (RF) electronics, and broadband terahertz (THz) detection at room temperature, including THz – energy harvesting. Despite these advantages, the lack of reliable physics-based compact models has prevented GFETs from moving into circuit-level design and industrial exploitation.

Accurate compact models are critical to capture the unique physics of graphene, predict device behavior under realistic conditions, and enable integration into commercial Electronic Design Automation (EDA) tools.

This PhD project will address this bottleneck by advancing a physics-based GFET compact model implemented in Verilog-A. The research will incorporate key physical effects such as electrolytic gating, temperature dependence, variability, and reliability, aligned with application-specific requirements. Targeted applications include hybrid CMOS–GFET biosensors, where standard CMOS models can accurately describe the CMOS circuitry, but reliable GFET compact models are essential to capture the behavior of the graphene transistor component, including sensitivity and selectivity; analog/RF circuits, where the intrinsic ambipolarity of GFETs enables multifunctional operation; and THz detection, where GFETs provide a competitive alternative to silicon and III–V devices. Experimental datasets from fabrication partners will support parameter extraction, iterative calibration, and benchmarking against industrial GFET processes.

The candidate will validate the improved model with experimental results and apply it to simulate reference GFET-based circuits, demonstrating predictive accuracy and robustness. In addition, the project will contribute to broader design enablement activities, including support for interoperability with commercial design tools and participation in the development of a graphene Process Design Kit (PDK) together with industrial partners.

The expected outcome is a validated, industry-compatible GFET compact modeling framework that will accelerate the design of GFET-based integrated circuits, with emphasis on biosensing, RF, and THz applications. The candidate will acquire expertise in device modeling, experimental characterization, circuit simulation, and design-technology co-optimization, positioning them at the interface of academic research and industrial innovation.

Candidates should hold a Master’s degree in Electronic Engineering, Physics, Materials Science, or a related field, with strong academic performance. A solid background in semiconductor devices, nanoelectronics, or advanced transistor physics is essential. Experience with compact modeling, Verilog-A, SPICE, or other circuit simulation tools is desirable. Familiarity with device characterization (DC, AC, RF, or noise measurements) and programming skills (MATLAB, Python, or similar) are required for model development and data analysis.

The candidate should work collaboratively with experimental teams and industrial partners, communicate effectively in English, and demonstrate motivation for interdisciplinary research bridging device physics and circuits. Attention to detail, problem-solving, and a proactive approach to simulation and experimental challenges are expected.

The research group led by Prof. David Jiménez at the Department of Electronic Engineering, UAB, is internationally recognized for its expertise in the compact modeling and characterization of graphene and other 2D-material-based transistors (GFETs/2D-FETs). Its work focuses on the development of physics-based compact models implemented in Verilog-A, enabling predictive simulations of DC, AC, transient, noise, and variability effects, which are indispensable for circuit design and industrial exploitation. A strong emphasis is placed on experimental validation and parameter extraction methods to ensure accurate representation of device behavior under realistic conditions.

The group has a leading role in major European initiatives, including the Graphene Flagship and the GraphCAT project, and actively contributes to the creation of the first commercial GFET simulation platforms and design tools. It collaborates with prestigious universities, research centers, and industry worldwide, bridging fundamental advances with technology transfer.